TechXplore: Researchers mine cache of Intel processors to speed up data packet processing

By | Media Coverage

Developed with Ericsson Research, the slice-aware memory-management scheme allows frequently used data to be accessed more quickly via the last-level cache of memory (LLC) of an Intel Xeon CPU. By establishing a key-value store and allocating memory in a way that it maps to the most appropriate LLC slice, they demonstrated both high-speed packet processing and improved performance of a key-value store.

Read the full article at: https://techxplore.com/news/2019-07-cache-intel-processors-packet.html