diff mbox

[dpdk-dev] i40e: fix the write flush in vf driver

Message ID 1447657710-10563-1-git-send-email-jingjing.wu@intel.com (mailing list archive)
State Accepted, archived
Headers

Commit Message

Jingjing Wu Nov. 16, 2015, 7:08 a.m. UTC 
  For i40e vf driver, should use I40EVF_WRITE_FLUSH to flush
configuration but not I40E_WRITE_FLUSH. This patch fixed this issue.

Fixes: be6c228d4da3 (i40evf: support Rx interrupt)

Reported-by: Qian Xu <qian.q.xu@intel.com>
Signed-off-by: Jingjing Wu <jingjing.wu@intel.com>
---
 drivers/net/i40e/i40e_ethdev_vf.c | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

Comments

Zhang, Helin Nov. 16, 2015, 7:19 a.m. UTC | #1 
-----Original Message-----
From: Wu, Jingjing 
Sent: Monday, November 16, 2015 3:09 PM
To: dev@dpdk.org
Cc: Wu, Jingjing; Zhang, Helin; Liang, Cunming; Xu, Qian Q
Subject: [PATCH] i40e: fix the write flush in vf driver

For i40e vf driver, should use I40EVF_WRITE_FLUSH to flush configuration but not I40E_WRITE_FLUSH. This patch fixed this issue.

Fixes: be6c228d4da3 (i40evf: support Rx interrupt)

Reported-by: Qian Xu <qian.q.xu@intel.com>
Signed-off-by: Jingjing Wu <jingjing.wu@intel.com>
Acked-by: Helin Zhang <helin.zhang@intel.com>
Thomas Monjalon Nov. 23, 2015, 10:29 p.m. UTC | #2 
> For i40e vf driver, should use I40EVF_WRITE_FLUSH to flush configuration but not I40E_WRITE_FLUSH. This patch fixed this issue.
> 
> Fixes: be6c228d4da3 (i40evf: support Rx interrupt)
> 
> Reported-by: Qian Xu <qian.q.xu@intel.com>
> Signed-off-by: Jingjing Wu <jingjing.wu@intel.com>
> Acked-by: Helin Zhang <helin.zhang@intel.com>

Applied, thanks
diff mbox

Patch

diff --git a/drivers/net/i40e/i40e_ethdev_vf.c b/drivers/net/i40e/i40e_ethdev_vf.c
index 7ce8687..ea96f85 100644
--- a/drivers/net/i40e/i40e_ethdev_vf.c
+++ b/drivers/net/i40e/i40e_ethdev_vf.c
@@ -1700,7 +1700,7 @@  i40evf_enable_queues_intr(struct rte_eth_dev *dev)
 			       I40E_VFINT_DYN_CTL01,
 			       I40E_VFINT_DYN_CTL01_INTENA_MASK |
 			       I40E_VFINT_DYN_CTL01_CLEARPBA_MASK);
-		I40E_WRITE_FLUSH(hw);
+		I40EVF_WRITE_FLUSH(hw);
 		return;
 	}
 
@@ -1716,7 +1716,7 @@  i40evf_enable_queues_intr(struct rte_eth_dev *dev)
 				I40E_VFINT_DYN_CTL01_INTENA_MASK |
 				I40E_VFINT_DYN_CTL01_CLEARPBA_MASK);
 
-	I40E_WRITE_FLUSH(hw);
+	I40EVF_WRITE_FLUSH(hw);
 }
 
 static inline void
@@ -1728,7 +1728,7 @@  i40evf_disable_queues_intr(struct rte_eth_dev *dev)
 
 	if (!rte_intr_allow_others(intr_handle)) {
 		I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01, 0);
-		I40E_WRITE_FLUSH(hw);
+		I40EVF_WRITE_FLUSH(hw);
 		return;
 	}
 
@@ -1740,7 +1740,7 @@  i40evf_disable_queues_intr(struct rte_eth_dev *dev)
 	else
 		I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01, 0);
 
-	I40E_WRITE_FLUSH(hw);
+	I40EVF_WRITE_FLUSH(hw);
 }
 
 static int
@@ -1770,7 +1770,7 @@  i40evf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
 			       (interval <<
 				I40E_VFINT_DYN_CTLN1_INTERVAL_SHIFT));
 
-	I40E_WRITE_FLUSH(hw);
+	I40EVF_WRITE_FLUSH(hw);
 
 	rte_intr_enable(&dev->pci_dev->intr_handle);
 
@@ -1793,7 +1793,7 @@  i40evf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
 						    I40E_RX_VEC_START),
 			       0);
 
-	I40E_WRITE_FLUSH(hw);
+	I40EVF_WRITE_FLUSH(hw);
 
 	return 0;
 }