diff mbox

[dpdk-dev,16/32] net/dpaa2: dpio add support to check SOC type

Message ID 1480875447-23680-17-git-send-email-hemant.agrawal@nxp.com (mailing list archive)
State Changes Requested, archived
Delegated to: Ferruh Yigit
Headers

Checks

Context Check Description
checkpatch/checkpatch warning coding style issues

Commit Message

Hemant Agrawal Dec. 4, 2016, 6:17 p.m. UTC 
  Signed-off-by: Hemant Agrawal <hemant.agrawal@nxp.com>
---
 drivers/net/dpaa2/base/dpaa2_hw_dpio.c | 74 ++++++++++++++++++++++++++++++++++
 1 file changed, 74 insertions(+)

Comments

Jerin Jacob Dec. 15, 2016, 6:34 a.m. UTC | #1 
On Sun, Dec 04, 2016 at 11:47:11PM +0530, Hemant Agrawal wrote:
> Signed-off-by: Hemant Agrawal <hemant.agrawal@nxp.com>
> ---
>  drivers/net/dpaa2/base/dpaa2_hw_dpio.c | 74 ++++++++++++++++++++++++++++++++++
>  1 file changed, 74 insertions(+)
> 
> diff --git a/drivers/net/dpaa2/base/dpaa2_hw_dpio.c b/drivers/net/dpaa2/base/dpaa2_hw_dpio.c
> index 9c6eb96..3b8f87d 100644
> --- a/drivers/net/dpaa2/base/dpaa2_hw_dpio.c
> +++ b/drivers/net/dpaa2/base/dpaa2_hw_dpio.c
> @@ -70,6 +70,18 @@
>  static struct dpio_device_list *dpio_dev_list; /*!< DPIO device list */
>  static uint32_t io_space_count;
>  
> +#define ARM_CORTEX_A53		0xD03
> +#define ARM_CORTEX_A57		0xD07
> +#define ARM_CORTEX_A72		0xD08

May not be good idea to have generic ARM part number definition in driver
file.

> +
> +static int dpaa2_soc_core = ARM_CORTEX_A72;
> +
> +#define NXP_LS2085	1
> +#define NXP_LS2088	2
> +#define NXP_LS1088	3
> +
> +static int dpaa2_soc_family  = NXP_LS2088;
> +
>  /*Stashing Macros default for LS208x*/
>  static int dpaa2_core_cluster_base = 0x04;
>  static int dpaa2_cluster_sz = 2;
> @@ -101,6 +113,58 @@
>  	return dpaa2_core_cluster_base + x;
>  }
>  
> +static int cpuinfo_arm(FILE *file)
> +{
> +	char str[128], *pos;
> +	int part = -1;
> +
> +	#define ARM_CORTEX_A53_INFO	"Cortex-A53"
> +	#define ARM_CORTEX_A57_INFO	"Cortex-A57"
> +	#define ARM_CORTEX_A72_INFO	"Cortex-A72"
> +
> +	while (fgets(str, sizeof(str), file) != NULL) {
> +		if (part >= 0)
> +			break;
> +		pos = strstr(str, "CPU part");
> +		if (pos != NULL) {
> +			pos = strchr(pos, ':');
> +			if (pos != NULL)
> +				sscanf(++pos, "%x", &part);
> +		}
> +	}
> +
> +	dpaa2_soc_core = part;
> +	if (part == ARM_CORTEX_A53) {
> +		dpaa2_soc_family = NXP_LS1088;
> +		printf("\n########## Detected NXP LS108x with %s\n",
> +		       ARM_CORTEX_A53_INFO);
> +	} else if (part == ARM_CORTEX_A57) {
> +		dpaa2_soc_family = NXP_LS2085;
> +		printf("\n########## Detected NXP LS208x Rev1.0 with %s\n",
> +		       ARM_CORTEX_A57_INFO);
> +	} else if (part == ARM_CORTEX_A72) {
> +		dpaa2_soc_family = NXP_LS2088;
> +		printf("\n########## Detected NXP LS208x with %s\n",
> +		       ARM_CORTEX_A72_INFO);
> +	}
> +	return 0;
> +}
> +
> +static void
> +check_cpu_part(void)
> +{
> +	FILE *stream;
> +
> +	stream = fopen("/proc/cpuinfo", "r");
> +	if (!stream) {
> +		PMD_INIT_LOG(WARNING, "Unable to open /proc/cpuinfo\n");
> +		return;
> +	}
> +	cpuinfo_arm(stream);
> +
> +	fclose(stream);
> +}
> +
>  static int
>  configure_dpio_qbman_swp(struct dpaa2_dpio_dev *dpio_dev)
>  {
> @@ -326,6 +390,16 @@ static inline struct dpaa2_dpio_dev *dpaa2_get_qbman_swp(void)
>  {
>  	struct dpaa2_dpio_dev *dpio_dev;
>  	struct vfio_region_info reg_info = { .argsz = sizeof(reg_info)};
> +	static int first_time;
> +
> +	if (!first_time) {
> +		check_cpu_part();
> +		if (dpaa2_soc_family == NXP_LS1088) {
> +			dpaa2_core_cluster_base = 0x02;
> +			dpaa2_cluster_sz = 4;
Can this device configuration information passed through dt/the means
where you are populating the fsl bus for dpio ?

if not arm64 cpu part identification code can go in arm64 common
code. Even better if we have EAL API for same. Looks like x86 similar
attribute called "model"
Hemant Agrawal Dec. 15, 2016, 7:01 a.m. UTC | #2 
On 12/15/2016 12:04 PM, Jerin Jacob wrote:
> On Sun, Dec 04, 2016 at 11:47:11PM +0530, Hemant Agrawal wrote:
>> Signed-off-by: Hemant Agrawal <hemant.agrawal@nxp.com>
>> ---
>>  drivers/net/dpaa2/base/dpaa2_hw_dpio.c | 74 ++++++++++++++++++++++++++++++++++
>>  1 file changed, 74 insertions(+)
>>
>> diff --git a/drivers/net/dpaa2/base/dpaa2_hw_dpio.c b/drivers/net/dpaa2/base/dpaa2_hw_dpio.c
>> index 9c6eb96..3b8f87d 100644
>> --- a/drivers/net/dpaa2/base/dpaa2_hw_dpio.c
>> +++ b/drivers/net/dpaa2/base/dpaa2_hw_dpio.c
>> @@ -70,6 +70,18 @@
>>  static struct dpio_device_list *dpio_dev_list; /*!< DPIO device list */
>>  static uint32_t io_space_count;
>>
>> +#define ARM_CORTEX_A53		0xD03
>> +#define ARM_CORTEX_A57		0xD07
>> +#define ARM_CORTEX_A72		0xD08
>
> May not be good idea to have generic ARM part number definition in driver
> file.
>
>> +
>> +static int dpaa2_soc_core = ARM_CORTEX_A72;
>> +
>> +#define NXP_LS2085	1
>> +#define NXP_LS2088	2
>> +#define NXP_LS1088	3
>> +
>> +static int dpaa2_soc_family  = NXP_LS2088;
>> +
>>  /*Stashing Macros default for LS208x*/
>>  static int dpaa2_core_cluster_base = 0x04;
>>  static int dpaa2_cluster_sz = 2;
>> @@ -101,6 +113,58 @@
>>  	return dpaa2_core_cluster_base + x;
>>  }
>>
>> +static int cpuinfo_arm(FILE *file)
>> +{
>> +	char str[128], *pos;
>> +	int part = -1;
>> +
>> +	#define ARM_CORTEX_A53_INFO	"Cortex-A53"
>> +	#define ARM_CORTEX_A57_INFO	"Cortex-A57"
>> +	#define ARM_CORTEX_A72_INFO	"Cortex-A72"
>> +
>> +	while (fgets(str, sizeof(str), file) != NULL) {
>> +		if (part >= 0)
>> +			break;
>> +		pos = strstr(str, "CPU part");
>> +		if (pos != NULL) {
>> +			pos = strchr(pos, ':');
>> +			if (pos != NULL)
>> +				sscanf(++pos, "%x", &part);
>> +		}
>> +	}
>> +
>> +	dpaa2_soc_core = part;
>> +	if (part == ARM_CORTEX_A53) {
>> +		dpaa2_soc_family = NXP_LS1088;
>> +		printf("\n########## Detected NXP LS108x with %s\n",
>> +		       ARM_CORTEX_A53_INFO);
>> +	} else if (part == ARM_CORTEX_A57) {
>> +		dpaa2_soc_family = NXP_LS2085;
>> +		printf("\n########## Detected NXP LS208x Rev1.0 with %s\n",
>> +		       ARM_CORTEX_A57_INFO);
>> +	} else if (part == ARM_CORTEX_A72) {
>> +		dpaa2_soc_family = NXP_LS2088;
>> +		printf("\n########## Detected NXP LS208x with %s\n",
>> +		       ARM_CORTEX_A72_INFO);
>> +	}
>> +	return 0;
>> +}
>> +
>> +static void
>> +check_cpu_part(void)
>> +{
>> +	FILE *stream;
>> +
>> +	stream = fopen("/proc/cpuinfo", "r");
>> +	if (!stream) {
>> +		PMD_INIT_LOG(WARNING, "Unable to open /proc/cpuinfo\n");
>> +		return;
>> +	}
>> +	cpuinfo_arm(stream);
>> +
>> +	fclose(stream);
>> +}
>> +
>>  static int
>>  configure_dpio_qbman_swp(struct dpaa2_dpio_dev *dpio_dev)
>>  {
>> @@ -326,6 +390,16 @@ static inline struct dpaa2_dpio_dev *dpaa2_get_qbman_swp(void)
>>  {
>>  	struct dpaa2_dpio_dev *dpio_dev;
>>  	struct vfio_region_info reg_info = { .argsz = sizeof(reg_info)};
>> +	static int first_time;
>> +
>> +	if (!first_time) {
>> +		check_cpu_part();
>> +		if (dpaa2_soc_family == NXP_LS1088) {
>> +			dpaa2_core_cluster_base = 0x02;
>> +			dpaa2_cluster_sz = 4;
> Can this device configuration information passed through dt/the means
> where you are populating the fsl bus for dpio ?
>
> if not arm64 cpu part identification code can go in arm64 common
> code. Even better if we have EAL API for same. Looks like x86 similar
> attribute called "model"
>

This is good idea to have something equivalent in EAL. let me try to 
make an attempt on it.
diff mbox

Patch

diff --git a/drivers/net/dpaa2/base/dpaa2_hw_dpio.c b/drivers/net/dpaa2/base/dpaa2_hw_dpio.c
index 9c6eb96..3b8f87d 100644
--- a/drivers/net/dpaa2/base/dpaa2_hw_dpio.c
+++ b/drivers/net/dpaa2/base/dpaa2_hw_dpio.c
@@ -70,6 +70,18 @@ 
 static struct dpio_device_list *dpio_dev_list; /*!< DPIO device list */
 static uint32_t io_space_count;
 
+#define ARM_CORTEX_A53		0xD03
+#define ARM_CORTEX_A57		0xD07
+#define ARM_CORTEX_A72		0xD08
+
+static int dpaa2_soc_core = ARM_CORTEX_A72;
+
+#define NXP_LS2085	1
+#define NXP_LS2088	2
+#define NXP_LS1088	3
+
+static int dpaa2_soc_family  = NXP_LS2088;
+
 /*Stashing Macros default for LS208x*/
 static int dpaa2_core_cluster_base = 0x04;
 static int dpaa2_cluster_sz = 2;
@@ -101,6 +113,58 @@ 
 	return dpaa2_core_cluster_base + x;
 }
 
+static int cpuinfo_arm(FILE *file)
+{
+	char str[128], *pos;
+	int part = -1;
+
+	#define ARM_CORTEX_A53_INFO	"Cortex-A53"
+	#define ARM_CORTEX_A57_INFO	"Cortex-A57"
+	#define ARM_CORTEX_A72_INFO	"Cortex-A72"
+
+	while (fgets(str, sizeof(str), file) != NULL) {
+		if (part >= 0)
+			break;
+		pos = strstr(str, "CPU part");
+		if (pos != NULL) {
+			pos = strchr(pos, ':');
+			if (pos != NULL)
+				sscanf(++pos, "%x", &part);
+		}
+	}
+
+	dpaa2_soc_core = part;
+	if (part == ARM_CORTEX_A53) {
+		dpaa2_soc_family = NXP_LS1088;
+		printf("\n########## Detected NXP LS108x with %s\n",
+		       ARM_CORTEX_A53_INFO);
+	} else if (part == ARM_CORTEX_A57) {
+		dpaa2_soc_family = NXP_LS2085;
+		printf("\n########## Detected NXP LS208x Rev1.0 with %s\n",
+		       ARM_CORTEX_A57_INFO);
+	} else if (part == ARM_CORTEX_A72) {
+		dpaa2_soc_family = NXP_LS2088;
+		printf("\n########## Detected NXP LS208x with %s\n",
+		       ARM_CORTEX_A72_INFO);
+	}
+	return 0;
+}
+
+static void
+check_cpu_part(void)
+{
+	FILE *stream;
+
+	stream = fopen("/proc/cpuinfo", "r");
+	if (!stream) {
+		PMD_INIT_LOG(WARNING, "Unable to open /proc/cpuinfo\n");
+		return;
+	}
+	cpuinfo_arm(stream);
+
+	fclose(stream);
+}
+
 static int
 configure_dpio_qbman_swp(struct dpaa2_dpio_dev *dpio_dev)
 {
@@ -326,6 +390,16 @@  static inline struct dpaa2_dpio_dev *dpaa2_get_qbman_swp(void)
 {
 	struct dpaa2_dpio_dev *dpio_dev;
 	struct vfio_region_info reg_info = { .argsz = sizeof(reg_info)};
+	static int first_time;
+
+	if (!first_time) {
+		check_cpu_part();
+		if (dpaa2_soc_family == NXP_LS1088) {
+			dpaa2_core_cluster_base = 0x02;
+			dpaa2_cluster_sz = 4;
+		}
+		first_time = 1;
+	}
 
 	if (obj_info->num_regions < NUM_DPIO_REGIONS) {
 		PMD_INIT_LOG(ERR, "ERROR, Not sufficient number "