diff mbox

[dpdk-dev,v2] ixgbe: prefetch cacheline after pointer becomes valid

Message ID 1443203091-22306-1-git-send-email-zoltan.kiss@linaro.org (mailing list archive)
State Accepted, archived
Headers

Commit Message

Zoltan Kiss Sept. 25, 2015, 5:44 p.m. UTC 
  At the original point the rx_pkts[pos( + n)] pointers are not initialized, so
the code is prefetching random data.

Signed-off-by: Zoltan Kiss <zoltan.kiss@linaro.org>
---
v2: fixing tabs

Comments

Bruce Richardson Sept. 28, 2015, 9:53 a.m. UTC | #1 
On Fri, Sep 25, 2015 at 10:44:51AM -0700, Zoltan Kiss wrote:
> At the original point the rx_pkts[pos( + n)] pointers are not initialized, so
> the code is prefetching random data.
> 
> Signed-off-by: Zoltan Kiss <zoltan.kiss@linaro.org>

Acked-by: Bruce Richardson <bruce.richardson@intel.com>
Thomas Monjalon Oct. 28, 2015, 4:19 p.m. UTC | #2 
2015-09-28 10:53, Bruce Richardson:
> On Fri, Sep 25, 2015 at 10:44:51AM -0700, Zoltan Kiss wrote:
> > At the original point the rx_pkts[pos( + n)] pointers are not initialized, so
> > the code is prefetching random data.
> > 
> > Signed-off-by: Zoltan Kiss <zoltan.kiss@linaro.org>
> 
> Acked-by: Bruce Richardson <bruce.richardson@intel.com>

Applied, thanks
diff mbox

Patch

diff --git a/drivers/net/ixgbe/ixgbe_rxtx_vec.c b/drivers/net/ixgbe/ixgbe_rxtx_vec.c
index 3c6d8c5..ccd93c7 100644
--- a/drivers/net/ixgbe/ixgbe_rxtx_vec.c
+++ b/drivers/net/ixgbe/ixgbe_rxtx_vec.c
@@ -284,13 +284,6 @@  _recv_raw_pkts_vec(struct ixgbe_rx_queue *rxq, struct rte_mbuf **rx_pkts,
 		__m128i zero, staterr, sterr_tmp1, sterr_tmp2;
 		__m128i mbp1, mbp2; /* two mbuf pointer in one XMM reg. */
 
-		if (split_packet) {
-			rte_prefetch0(&rx_pkts[pos]->cacheline1);
-			rte_prefetch0(&rx_pkts[pos + 1]->cacheline1);
-			rte_prefetch0(&rx_pkts[pos + 2]->cacheline1);
-			rte_prefetch0(&rx_pkts[pos + 3]->cacheline1);
-		}
-
 		/* B.1 load 1 mbuf point */
 		mbp1 = _mm_loadu_si128((__m128i *)&sw_ring[pos]);
 
@@ -312,6 +305,13 @@  _recv_raw_pkts_vec(struct ixgbe_rx_queue *rxq, struct rte_mbuf **rx_pkts,
 		/* B.2 copy 2 mbuf point into rx_pkts  */
 		_mm_storeu_si128((__m128i *)&rx_pkts[pos+2], mbp2);
 
+		if (split_packet) {
+			rte_prefetch0(&rx_pkts[pos]->cacheline1);
+			rte_prefetch0(&rx_pkts[pos + 1]->cacheline1);
+			rte_prefetch0(&rx_pkts[pos + 2]->cacheline1);
+			rte_prefetch0(&rx_pkts[pos + 3]->cacheline1);
+		}
+
 		/* A* mask out 0~3 bits RSS type */
 		descs[3] = _mm_and_si128(descs0[3], desc_mask);
 		descs[2] = _mm_and_si128(descs0[2], desc_mask);